Power amplifiers are commonly used in audio applications as speaker drivers. Such applications may include consumer, automotive or portable electronic devices. A specific type of power amplifier is the so-called class D amplifier. Class-D amplifiers are switched mode amplifiers whereby the output is switched between a supply rail voltage and ground by employing pulse width modulation (PWM) techniques. In power amplifiers it is customary to arrange two power transistors in series to form an output or end stage. The end stage is then connected to, for example in the case of audio applications, a speaker.
FIG. 1 illustrates a simplified schematic of a class-D amplifier output stage, also known as an end stage. It consists of two complimentary power field effect transistors (FETs) ML, MH, and control logic for generating driving signals to control gate drivers. Here the gate drivers control the gate voltages VLH, VGL of the power FETs ML, MH. The gate drivers enable switching of the output stage and accurate control of the rate of change of the output voltage VOUT during switching. Such control can ensure minimal or zero deadtime as disclosed in U.S. Pat. No. 7,271,655, the contents of which are incorporated herein by reference. Typically such power FETs have large gate capacitances due to the requirement that they need to be switched quickly. Therefore the gate drivers need to be able to source and sink very high peak currents.
Typically gate drivers can be implemented as CMOS invertors using FETs, as illustrated in FIG. 2. The peak currents that the gate drivers are required to source or sink are drawn from the main power supply VSUP and ground VGND of the amplifier. Because, the gate drivers need to be able to source and sink very high peak currents the gate drivers have an effect on the switching capabilities of the output stage. It therefore follows that the FETs forming the gate drivers MHN/HP, MLN/LP must be sized, that is the length and width of the FETs must be designed, appropriately for the specific amplifier application.
For the arrangement of FIG. 2, due to the requirement that the gates of the power FETs ML, MH are switched between the supply VSUP and ground VGND of the amplifier, the supply voltage cannot exceed the maximum allowed gate source voltage rating of the FETs forming the gate drivers MHN/HP, MLN/LP. Following this and taking mobile device applications as an example, the class-D amplifier used for driving internal speakers and headphone outputs is connected directly to the device battery (typically for example 5.5V maximum) in order to maximise output power. If it is necessary to increase the supply voltage a DC-DC booster can be used.
A typical power FET used in such a design can have a drain source breakdown voltage greater than 20V, whereas the maximum gate-source voltage of the power FET is typically in the order of 3.3V. Therefore, if the drain-source breakdown of the power FETs is 20V, it would be possible to use a supply voltage of 20V. However, with the arrangement of FIG. 2, the supply voltage 20V would also appear between the gate and source of the power FETs that is rated up to 3.3V. Therefore, because the gate driver will not be able to source or sink large peak currents and the maximum gate source voltage of the power FETs will be above that of the gate driver FETs, exceeding this maximum could irreparably damage the gate driver.
An alternative arrangement is shown in FIG. 3 that does not have issues associated with the arrangement of FIG. 2 because the gate drivers use a separate lower auxiliary supply voltage. Due to the separate auxiliary supply, the voltage that appears across the gate-source of the power FETs is limited such that it cannot exceed the supply voltage of the gate driver.
These auxiliary supplies could be implemented using two separate supply voltages VREGN, VREGP, one each for the lowside and highside gate drivers. The supply voltages can be generated using voltage regulators integrated on an amplifier chip. However, because of the requirement to source or sink large peak currents external decoupling capacitors CREGP, CREGN are required to supply the large peak currents. The additional components required to implement this solution may increase die area and costs.
A gate driver architecture is described that limits the maximum gate voltage of power transistors to a safe value that is lower than the supply voltage.